| 摘要 |
A device comprises an integrated circuit having first and second domains, the first domain having a first clock boundary module; and the second domain having a second clock boundary module. The first clock boundary module comprises: a buffer, for storing data for transfer to the second domain; and a first controller operable to send a first control signal to the second clock boundary module via a first synchroniser, the first control signal indicating the presence of a packet of data in a first storage location of the buffer. One of the first and second clock boundary modules comprises a multiplexer having an input connected to an output of the buffer and an output connected to circuitry forming part of the second domain. The second clock boundary module comprises: a second controller, operable in response to receiving the first control signal to control transfer of said data from the buffer by the multiplexer, and to send a second control signal to the first controller via a second synchroniser, the second control signal indicating transfer of said data.
|
