Interference pulses suppression circuit for use in digital circuit, has gate producing output signal at output terminal that is connected with output, where level of output signal corresponds to level of signals applied at input terminals

摘要

The circuit (1) has a gate (4) receiving a signal at an input (2) at an input terminal (5), where the signal is delayed about double the times of a time delay. The gate receives another signal applied at the input at another input terminal (6), where the latter signal is delayed about the delay. The gate receives a third signal, which is undelayed and applied at the input at third input terminal (7). The gate produces an output signal at an output terminal (8) connected with an output (3), where a level of the output signal corresponds to a level of the signals applied at the input terminals. An independent claim is also included for a digital circuit implemented on a silicon substrate, comprising a logic switch.