| 摘要 |
<p>Provided is a parallel CAM capable of performing a parity check at high speed during search. A CAM (10) searches through all the addresses at the same time and determines if the same data as inputted data is stored, and comprises a write/search parity generator (12) for generating respective parities (WP, SP) of n-bit write data (WD) and n-bit search data (SD), a plurality of memory locations (14) corresponding to a plurality of addresses, and a NAND circuit (16) for activating a parity error signal (PE) when at least one of valid parity coincidence signals (PMV) outputted from the memory locations (14) is inactive. Each of the memory locations (14) includes n data memory cells (2), a parity memory cell (3), an exclusive OR circuit (20) for determining if the parity (SP) and a parity (RP) coincide with each other and activating a parity coincidence signal (/PM) when the parities coincide, and a NAND circuit (22) for validating the parity coincidence signal (/PM) in response to a data coincidence signal (DML).</p> |
