High speed circuit and a method to test memory address uniqueness

摘要

A circuit and method for testing address uniqueness of a memory array are disclosed. The circuit includes a plurality of current sinks associated with rows and columns of the memory array. A plurality of word lines of the memory array are coupled to the plurality of current sinks. A current mirror circuit is coupled to the plurality of current sinks and a circuit output node is coupled to the current mirror circuit. The circuit output node is configured to compare a total current from tested word lines of the memory array with a predetermined reference current, and to output a test pass or test fail indication in response to the comparison.