| 摘要 |
An apparatus for controlling an active cycle of semiconductor memory that supports a synchronous mode and an asynchronous mode is provided. The apparatus includes an operational mode control unit that determines the operational mode of the semiconductor memory on the basis of a clock signal for a predetermined time and outputs an operational mode determination signal, and an active control unit that controls the output of an active signal for executing an active cycle of the corresponding operational mode on the basis of the operational mode determination signal.
|
