| 摘要 |
A bus control apparatus includes a plurality of blocks configured to output a write command for writing data into memory via a bus, and a bus connection control unit provided in correspondence with each of the blocks. The bus connection control unit monitors signals between the bus and the block, and upon detecting a read command signal for reading data in a cause register of the block, blocks connection of a signal line between the block and the bus and outputs a dummy read command signal for the memory. The bus connection control unit releases blockage when a response signal for the dummy read command signal is received.
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