发明名称 |
Register alias table cache to map a logical register to a physical register |
摘要 |
Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. In one embodiment, an apparatus may comprise a register alias table cache to map a logical register to a physical register. The register alias table cache may have a capacity corresponding to a subset of architectural logical registers. The apparatus may further comprise store logic coupled to the cache to perform operations to save an existing content of the physical register if a cache entry corresponding to the logical register is evicted from the cache. The apparatus may also comprise load logic coupled to the cache to perform operations to load a content to the physical register and to form a new entry in the cache if a needed mapping is not present in the cache. |
申请公布号 |
US7711898(B2) |
申请公布日期 |
2010.05.04 |
申请号 |
US20030737760 |
申请日期 |
2003.12.18 |
申请人 |
INTEL CORPORATION |
发明人 |
SODANI AVINASH;JOURDAN STEPHAN J.;SAMAAN SAMIE B. |
分类号 |
G06F12/00;G06F9/00;G06F9/38 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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