| 摘要 |
A sigma-delta digital to analog converter (DAC) module converts the digital input signal to the analog output signal through segmentation, including a primary and a secondary sigma-delta modulator. The primary sigma-delta modulator produces a primary digital segment and a primary quantization error. A primary sample is delayed, decoded, scrambled and converted to produce a primary analog segment. A secondary sigma-delta modulates the primary quantization error to produce a secondary digital segment which is noise shaped by a noise transfer function of the primary sigma-delta modulator to produce a noise shaped secondary digital segment which is decoded, scrambled, converted and scaled to produce a secondary analog segment. An adder combines the primary analog segment and the secondary analog segment to produce the analog output signal.
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