| 摘要 |
A memory access circuit is provided. The memory access circuit includes a latch circuit, a feedback reset circuit, and a gate latch circuit. The latch circuit receives a high level input signal and outputs a first signal. The feedback reset circuit generates a second signal and a reset signal according to the first signal. The gate latch circuit generates a pre-charge signal and an enable signal according to the first signal and the second signal. The memory is accessed according to the pre-charging signal and the enable signal.
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