| 摘要 |
PURPOSE: A delay control circuit of a semiconductor memory device is provided to accurately control a delay value by eliminating the parasitic effect of a switch. CONSTITUTION: A plurality of inverters(301,302) are formed between an input terminal and an output terminal. One side of a capacitor(306) is connected to the connecting point(DLY) between the inverters. NMOS transistors(303,304,305) are connected between the other one side of the capacitor and a ground power. A NMOS transistor on/off control signal corresponding to a trimming code value is inputted to a gate terminal of the NMOS transistor. An inverter connected to an input(IN) outputs the applied signal of the connecting point. The inverter connected to the connecting point generates a final output signal. The capacitor connected to the connecting point decides the slope of the connecting point. The NMOS transistor switches control the size of the capacitor. |
