| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a virtual address cache memory for reducing circuit amounts, and for solving an alias problem by implementing the function of a TLB on a cache memory. <P>SOLUTION: The virtual address cache memory 12 is provided with: a TLB virtual page memory 21 configured to retain entry data including a virtual page tag of predetermined high-order bits of a virtual address of a process, and output a hit signal when the virtual page tag matches the virtual page tag from a processor; a data memory 23 configured to retain cache data with the virtual page tag or a page offset as a cache index; and a cache state memory 24 configured to retain a cache state of the cache data stored in the data memory 23, in a manner corresponding to the cache index. <P>COPYRIGHT: (C)2010,JPO&INPIT |
