| 摘要 |
An amplifier (e.g., an LNA) with improved ESD protection circuitry is described. In one exemplary design, the amplifier includes a transistor, an inductor, and a clamp circuit. The transistor has a gate coupled to a pad and provides signal amplification for the amplifier. The inductor is coupled to a source of the transistor and provides source degeneration for the transistor. The clamp circuit is coupled between the gate and source of the transistor and provides ESD protection for the transistor. The clamp circuit may include at least one diode coupled between the gate and source of the transistor. The clamp circuit conducts current through the inductor to generate a voltage drop across the inductor when a large voltage pulse is applied to the pad. The gate-to-source voltage (Vgs) of the transistor is reduced by the voltage drop across the inductor, which may improve the reliability of the transistor.
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