| 摘要 |
A logic simulation apparatus includes: a jitter detector generation section 21 that generates information concerning a jitter circuit for determining whether a time variation occurs in signal passing between a first circuit and a second circuit, the first circuit configured to output a signal with a clock output from a predetermined clock source and the second circuit configured to output a signal with a clock output from a clock source different from the above predetermined clock source; and a constraint solver generation section 22 that generates information concerning a solver that is configured to create a signal to be output at an observation point using a logical expression of an output signal of the second circuit and output, based on the logical expression and output signal of the jitter detector circuit, a signal constrained by the output signal of the jitter detector circuit and output signal of the second circuit.
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