ARITHMETIC-LOGIC UNIT FOR DIGITAL SIGNAL PROCESSOR

摘要

The invention relates to an arithmetic-logic unit (ALU) for a digital signal processor (DSP), specifically for processing audio signals, comprising a multiplier circuit able to receive in input a first and a second signal and to supply in output a third signal which represents the result of the multiplication of said first and second signal, a generator circuit of a dither signal, a summation circuit downline of the multiplier circuit, said summation circuit being able to perform an addition operation between said third signal and the dither signal so as to supply a fourth signal in output, and a truncation or rounding circuit downline of the summation circuit, able to truncate or round said fourth signal.