发明名称 Write-side calibration for data interface
摘要 Circuits, methods and apparatus are provided to reduce skew among signals being provided or transmitted by a data interface. Signal path delays are varied such that signals transmitted by a memory interface are calibrated or aligned with each other along a rising and/or falling edge. For example, self-calibration, external circuitry, or design tools can provide skew adjustment of each output channel by determining one or more delays for each output channel path. When aligning multiple edges, the edges of the output signals may be aligned independently, e.g., using edge specific delay elements.
申请公布号 US7706996(B2) 申请公布日期 2010.04.27
申请号 US20070735394 申请日期 2007.04.13
申请人 ALTERA CORPORATION 发明人 CHONG YAN;SUNG CHIAKANG;HUANG JOSEPH;CHU MICHAEL H. M.
分类号 G06F11/00;G06F19/00 主分类号 G06F11/00
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