Method and apparatus for reduction of bit-line disturb and soft-erase in a trapped-charge memory

摘要

A method and device for trading off inhibit disturb against bit-line disturb in a non-volatile memory where a threshold shift per inhibit disturb is increased, a threshold shift per bit-line disturb is decreased and the total threshold shift over the expected lifetime of the non-volatile memory due to inhibit disturbs is approximately equalized with the total threshold shift over the expected lifetime of the non-volatile memory due to bit-line disturbs.