CYCLICAL REDUNDANCY CODE FOR USE IN A HIGH-SPEED SERIAL LINK
摘要
A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.
申请公布号
WO2010000623(A4)
申请公布日期
2010.04.22
申请号
WO2009EP57580
申请日期
2009.06.18
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED;DELL, TIMOTHY;GOWER, KEVIN;LASTRAS-MONTANO, LUIS