发明名称 IMPLANTATION METHOD FOR REDUCING THRESHOLD VOLTAGE FOR HIGH-K METAL GATE DEVICE
摘要 The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.
申请公布号 US2010096705(A1) 申请公布日期 2010.04.22
申请号 US20080253741 申请日期 2008.10.17
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 HUNG CHENG-LUNG;HOU YONG-TIAN;KU KEH-CHIANG;HUANG CHIEN-HAO
分类号 H01L29/78;H01L21/28 主分类号 H01L29/78
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