发明名称 |
EFFECTIVE ADDRESS CACHE MEMORY, PROCESSOR AND EFFECTIVE ADDRESS CACHING METHOD |
摘要 |
An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
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申请公布号 |
US2010100685(A1) |
申请公布日期 |
2010.04.22 |
申请号 |
US20090580732 |
申请日期 |
2009.10.16 |
申请人 |
KABUSHIHIKI KAISHA TOSHIBA |
发明人 |
KUROSAWA YASUHIKO;IWASA SHIGEAKI;MAEDA SEIJI;YOSHIDA NOBUHIRO;SAITO MITSUO;HAYASHI HIROO |
分类号 |
G06F12/08;G06F12/00;G06F12/10 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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