| 摘要 |
PROBLEM TO BE SOLVED: To provide a burst length control circuit and a semiconductor memory device using the same. SOLUTION: The burst length control circuit includes: a clock signal generating section that generates first and second internal clock signals from a clock signal in response to first and second burst signals, a control signal generating section that is driven in response to the first and second internal clock signals and that generates first and second control signals whose enable region is adjusted by the first and second burst signals upon read or write operation, and a burst end signal generating section that generates a burst end signal in response to the first and second burst signals. The first control signal is disabled in response to the burst end signal. COPYRIGHT: (C)2010,JPO&INPIT
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