A buffer management structure for processing systems is described. In one embodiment, the buffer management structure includes a storage module and a control module. The storage module includes a read position and can store a bit indicating a valid state of a transaction request in a write entry. The control module can receive an invalidation request and modify the bit to indicate an invalid state for the transaction request and discard the transaction request when the transaction request is in the read position.
申请公布号
WO2010017043(A9)
申请公布日期
2010.04.22
申请号
WO2009US51705
申请日期
2009.07.24
申请人
QUALCOMM INCORPORATED;SHEN, JIAN;LESTER, ROBERT, ALLAN