| 摘要 |
The configurable logic device comprises a plurality of configurable logic cells (2). A configurable logic cell comprises a plurality of multi-bit registers (20a, 20b, 20c, 20d). At least one is accessible both in a parallel and in a serial fashion. A functional unit (30) therein is coupled to two or more of the registers and comprises a chain of functional unit segments (31, 31′) that each comprise an AND gate (33) and a 1-bit full adder (32) receiving an output of the AND-gate. An output selection facility (50) provides an output signal of the configurable logic cell selected from two or more input signals. At least one of the input signals is provided by one of the multi-bit registers, and another by the functional unit.
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