| 摘要 |
The process comprises masking a thin silicon film layer (204) using a hard mask (206) with patterns for defining a ridge waveguide, P doped region and N doped region. The waveguide is present on edge of the silicon layer, and placed between the doped regions, where the edge waveguide occupies an intrinsic region of the thin layer. The P doped region, the intrinsic region and the N doped region constitutes a PIN diode structure, where one of the P doped region is formed in the edge and perpendicular to the substrate. The hard mask is formed by etching of a layer of hard mask. The process comprises masking a thin silicon film layer (204) using a hard mask (206) with patterns for defining a ridge waveguide, P doped region and N doped region. The waveguide is present on edge of the silicon layer, and placed between the doped regions, where the edge waveguide occupies an intrinsic region of the thin layer. The P doped region, the intrinsic region and the N doped region constitutes a PIN diode structure, where one of the P doped region is formed in the edge and perpendicular to the substrate. The hard mask is formed by etching of a layer of hard mask. The hard masking pattern has outer edges that define the waveguide edge, an internal slit that defines the region to be doped in the waveguide edge. The process further comprises forming a first resin mask on the hard mask, etching unmasked parts of the thin silicon layer to obtain the edge of the waveguide, removing the first resin mask, forming a second resin mask that masks the portions of the structure that is not doped, carrying out of P type doping of the non-masked parts of the thin silicon layer, removing a second resin mask, forming a third resin mask masking portions of the structure that is not doped, carrying out the N type doping of the non-masked parts by the thin layer of silicon, removing the third resin mask, and removing hard mask. The first resin mask covers the slit of the hard mask and is shrunk from the outer edges of the hard mask which define the waveguide edge. The second resin mask comprises a slit of which the edges are shrunk from the edges of the slit of the hard mask. The edge of the third mask of the resin on the side of the region to be N doped is shrunk from the corresponding edge of the hard mask. The N type doping is carried out by ion implantation of plasma along 0[deg] with respect to a vertical direction on SOI substrate for doping the side of waveguide edge adjacent to the N doped region. A complete etching of the parts of the hard mask is provided between the step of etching of the thin silicon layer and the removing step of the first resin mask. |
