发明名称 Timing analysis apparatus and method of timing analysis
摘要 A timing analysis apparatus in an integrated logical circuit according to the present invention includes a jitter information generation unit for generating period jitter information of an operational clock in response to a power supply/ground noise, a jitter information storage unit for storing the generated period jitter information, and a timing analysis unit for performing a timing analysis of the integrated logical circuit based on the stored period jitter information.
申请公布号 US7702009(B2) 申请公布日期 2010.04.20
申请号 US20060639291 申请日期 2006.12.15
申请人 NEC ELECTRONICS CORPORATION 发明人 AKIMOTO TETSUYA
分类号 H04Q1/20;G06F17/50;H01L21/82 主分类号 H04Q1/20
代理机构 代理人
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