发明名称 |
Bipolar and CMOS integration with reduced contact height |
摘要 |
Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.
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申请公布号 |
US7701015(B2) |
申请公布日期 |
2010.04.20 |
申请号 |
US20030596573 |
申请日期 |
2003.12.16 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HE ZHONG-XIANG;ORNER BRADLEY A.;RAMACHANDRAN VIDHYA;JOSEPH ALVIN J.;ST. ONGE STEPHEN A.;WANG PING-CHUAN |
分类号 |
H01L29/72;H01L21/768;H01L21/8249;H01L23/485;H01L23/538;H01L27/06 |
主分类号 |
H01L29/72 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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