METHOD OF FABRICATING INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE HAVING GATE METAL SILICIDE LAYER

摘要

PURPOSE: A method for manufacturing an integrated circuit semiconductor device is provided to form a gate metal silicide layer with a uniform height on a gate electrode by planarizing an interlayer insulation layer and a gate capping pattern. CONSTITUTION: Gate patterns(24, 74) including gate electrodes(23, 73) and gate capping patterns(22, 72) are formed on a semiconductor substrate(10). An interlayer insulation layer(30) is formed to insulate the gate patterns. The interlayer insulation layer and a gate capping pattern are etched to be planarized. A gate metal silicide layer is selectively formed on a gate electrode using a chemical mechanical polishing process.