| 摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a clock phase estimation apparatus which prevents estimation accuracy of a clock phase from being degraded even in a reception signal of a low roll-off rate. <P>SOLUTION: The clock phase estimation apparatus includes: a limiter 1 for individually performing limiter processing on an in-phase component and a quadrature component of a signal to be used for estimating a clock phase among signals obtained by performing quadrature detection on a reception signal; filters 2, 4 for performing waveform shaping using a filter of a higher roll-off rate than normal communication to extract a clock component individually from each signal after limiter processing; squaring devices 3, 5 for squaring the clock components extracted by the filters 2, 4, respectively; an adder 6 for adding squared values to define a result as a clock phase estimation signal; a DFT processor 7 for performing DFT processing on the clock phase estimation signal; and a phase calculator 8 for estimating the clock phase on the basis of the signal after DFT processing. <P>COPYRIGHT: (C)2010,JPO&INPIT |
