发明名称 TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS
摘要 Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
申请公布号 US2010095253(A1) 申请公布日期 2010.04.15
申请号 US20080250424 申请日期 2008.10.13
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 HOU YUNG-CHIN;CHENG YING-CHOU;LIU RU-GUN;LAI CHIH-MING;CHENG YI-KAN;LIN CHUNG-KAI;CHAO HSIAO-SHU;YEH PING-HENG;WU MIN-HONG;KU YAO-CHING;OU TSONG-HUA
分类号 G06F17/50 主分类号 G06F17/50
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