发明名称 Zur effizienten Ausführung vieler asynchronen Ereignisaufgaben geeigneter Prozessor
摘要 The counter 52 is set with an initial value of "1" and is a counter with a maximum value of "4". This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1, 2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value "4", and when the values match, sets the task switching signal chg_task_ex at a "High" value, so that the processing switches to the execution of the next task. <IMAGE>
申请公布号 DE69841526(D1) 申请公布日期 2010.04.15
申请号 DE1998641526 申请日期 1998.03.03
申请人 PANASONIC CORPORATION 发明人 TANAKA, TAKAHARU;MAENOBU, KYOSHI;YOSHIOKA, KOSUKE;HIRAI, MAKOTO;KIYOHARA, TOKUZO
分类号 G06F9/46;G06F9/30;G06F9/38;G06F9/48;H04N7/26;H04N7/50 主分类号 G06F9/46
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