DIFFERENTIAL SWITCH, D/A CONVERTER, SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMMUNICATION DEVICE

摘要

A differential switch circuit in which a first differential switch basic circuit (1) having a first common source node (N1) shared by transistors (TP121, TP122) and a second differential switch basic circuit (2) having a second common source node (N2) shared by the transistors (TP131, TP132) are connected in parallel is characterized in that the first common source node (N1) and the second common source node (N2) are alternately reset to a predetermined voltage in each clock cycle.