| 摘要 |
1,126,075. Automatic exchange systems. INTERNATIONAL STANDARD ELECTRIC CORP. 25 March, 1966 [31 March, 1965], No. 13278/66. Heading H4K. In a multistage switching network having an associated core memory for storing the free/busy states of each interstage link, the addresses, in the memory, of all links which have access to each other are mathematically related. Trunking and cross-points (Fig. 2).-The network is a degenerate one which connects 16 inlets to 4 outlets via four stages comprising respectively four, 4 x 3 ; three, 4 x 3 ; three, 3 x 2; and two, 3 x 2 reed relay matrices. Memory (Fig. 3).-This comprises five columns of cores of which the columns correspond respectively to network inlets, A-B stage links, BC links, CD links and network outlets, and each core in a column represents a single link, outlet or inlet. Each core has a unique address which is related to the addresses of those cores corresponding to accessible links by the relationship:- the symbols will be explained in the example below. Operation.-It is assumed that a calling inlet requires access to any one of the network's outlets. Route selection takes place by selecting, in turn, the first free AB link accessible from the inlet, the first free BC link accessible to the chosen AB link, and, the first free CD link accessible to the chosen BC link. It is not discussed what happens if a free link in one stage does not have access to a free link in the following stage. As an example of the use of the memory, the following will be assumed: outlet (or link) B<SP>1</SP>32 whose unique core address is 35 (Fig. 3) has so far been selected; B<SP>1</SP>32 is the second outlet (N=2) from a matrix of the B (or second) stage, which stage has a total of 9 (m x , x=i- 1) outlets; the A (or first) stage has a total of 12 outlets (m x , x= 1); the core address of the first AB link A<SP>1</SP>11 is 16 (=E); each matrix of the C (or third) stage (i= 3) has (a i = )2 outlets: consequently the address of the core of the first outlet from the C stage to which B<SP>1</SP>32 has access is given by i.e. link C<SP>1</SP>21. If this link is busy, i.e. if its core is in the " 1 " state, logic circuitry adds 1 to its address and then interrogates the core, i.e. core 40 corresponding to link C<SP>1</SP>22 at this address. The core address of the first possible D outlet, i.e. D<SP>1</SP>21. is then obtained in a similar manner. The " arithmetic " is performed by a so-called translator (Z, Fig. 1, not shown) which is linked to the memory and to a control circuit that is used for core interrogation and cross-point control. The translator may be of the wired logic or stored programme type. |
