发明名称 HOLD CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a hold circuit holding a peak voltage or a bottom voltage of input voltages varying with time. <P>SOLUTION: The hold circuit 10 includes an input terminal 20 inputting a voltage, an output terminal 22 outputting a held voltage, a reference voltage terminal 24 connecting to a ground voltage, an operational amplifier 30, a switch circuit 32, a capacitor 36, and an impedance converting circuit 38. In the switch circuit 32, one main electrode 34b and a gate electrode 34d are connected to a connection point 26, another main electrode 34a is equipped with an insulated gate type transistor 34 connected to an output terminal 30c of the operational amplifier 30, and a semiconductor well region of the insulated gate type transistor 34 is connected to the output terminal 22 through a bias electrode 34c. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010085328(A) 申请公布日期 2010.04.15
申请号 JP20080256713 申请日期 2008.10.01
申请人 TOYOTA CENTRAL R&D LABS INC;DENSO CORP 发明人 MIZUNO KENTARO;OTA NORIKAZU;OHIRA YOSHIE;MAKINO YASUAKI;ARIYOSHI HIROMI;NAGASE KAZUYOSHI
分类号 G01R19/04;H01L21/822;H01L27/04 主分类号 G01R19/04
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