发明名称 MEMORY CONTROL SYSTEM
摘要 <P>PROBLEM TO BE SOLVED: To quickly carry out decompression processing of a compressed program by using hardware when transferring the compressed program stored in a low-speed memory device to a high-speed memory device. Ž<P>SOLUTION: A reversibly compressed program is read from a program memory 2 as the low-speed memory device by a read DMAC 12 to be decompressed by a pipeline circuit 8. In the pipeline circuit 8, decompression is carried out by pipeline processing to prevent failure in following of input of the compressed data due to low speed of decompression processing. Thereby decompression processing of the compressed program read from the program memory 2 is carried out continuously, the program can be transferred from the program memory 2 to a main memory 3 as the high-speed memory device. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010086321(A) 申请公布日期 2010.04.15
申请号 JP20080255301 申请日期 2008.09.30
申请人 DIGITAL ELECTRONICS CORP 发明人 MAEKAWA TOSHIYUKI
分类号 G06F12/04;G06F12/06;G06F13/28 主分类号 G06F12/04
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