| 摘要 |
Disclosed is a circuit for performing SIMD multiply-accumulate operations, the circuitry is responsive to control signals to process data in parallel on multiple data elements. Instruction decoder circuitry is coupled to the data processing circuitry and generates the control signals from program instructions. The input to the instruction decoder circuitry is a single instruction (a repeating multiply-accumulate instruction) having as operands a first vector of input data elements, a second vector of coefficient data elements, and a scalar value indicating the number of the iterations required. The SIMD data processing circuitry performs the required number of iterations of the multiply-accumulate process, each iteration involving performance of N multiply-accumulate operations in parallel in order to produce N multiply-accumulate data elements. For each iteration, the SIMD data processing circuitry determines N input data elements from said first vector and a single coefficient data element from the second vector to be multiplied with each of the N input data elements. The N multiply-accumulate data elements produced in a final iteration of the multiply-accumulate process are then used to produce N multiply accumulate results. |
