发明名称 Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming
摘要 A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming. Control circuitry identifies exception instructions in the instruction stream and detects when the exception instructions have been committed. The second processing block receives signals from the control circuitry and suspends processing of an instruction in the second processing block until all preceding exception instructions have been committed.
申请公布号 US7698537(B2) 申请公布日期 2010.04.13
申请号 US20060641959 申请日期 2006.12.20
申请人 ARM LIMITED 发明人 AIRAUD CEDRIC DENIS ROBERT;VINCENT MELANIE EMANUELLE LUCIE;ORION LUC;LATAILLE NORBERT BERNARD EUGENE
分类号 G06F9/00 主分类号 G06F9/00
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