| 摘要 |
A non-volatile memory array for an FPGA comprises a plurality of memory cells arranged in rows and columns and divided into a plurality of row segments. The source of each non-volatile memory transistor in each segment is coupled together to a common source line. A column segment line is associated with each segment of the array, and is coupled to the drains of each non-volatile memory transistor in the segment. A segment select transistor is coupled between each column segment line and its associated column line, and a high-voltage driver transistor is coupled to each column line.
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