发明名称 INFORMATION PROCESSING APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To provide a mechanism for interrupting cache access to an unauthorized address from a processor with little overhead to a time required for the cache access. Ž<P>SOLUTION: A cache memory controls access to the cache memory 120 from a plurality of application groups 100 and 101 having different address ranges where access is allowed, and interrupts access to an unauthorized address. An ID is respectively attached to the respective application groups, a tag field of the cache memory is expanded, and the ID is recorded when cache fill is performed. Access control is performed by comparing an expanded tag field with an ID of an application group of an access source upon hit determination. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2010079765(A) 申请公布日期 2010.04.08
申请号 JP20080249483 申请日期 2008.09.29
申请人 RENESAS TECHNOLOGY CORP 发明人 NITO TAKUMI;TAKADA MASASHI
分类号 G06F12/08;G06F21/24 主分类号 G06F12/08
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