METHOD TO REDUCE THE RESET CURRENT OF PHASE CHANGE MEMORIES USING STRESS LINER LAYERS

摘要

A memory cell structure and method for forming the same. The method includes forming a via (112) within a dielectric layer (108, 110). The via is formed over the center of an electrically conducting bottom electrode (104). The method includes depositing a stress liner (202) along at least one sidewall of the via. The stress liner imparting stress on material proximate the stress liner. In one embodiment, the stress liner provides a stress in the range of 500 to 5000 MPa on the material enclosed within its volume. The method includes depositing phase change material (402) within the via and the volume enclosed by the stress liner. The method also includes forming an electrically conducting top electrode (502) above the phase change material.