| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an analog DLL circuit of a reduced circuit scale and a reduced power consumption which is a delay locked loop circuit, and controls a phase of a clock signal with respect to that of a reference clock signal. <P>SOLUTION: There is provided the delay locked loop circuit which includes: a phase comparator for outputting a signal according to the comparison result of a reference clock signal phase and a first clock signal phase; the initial phase difference detector for generating a selection signal according to the phase comparator output signal at an initial signal inputting time; an initial phase difference setting circuit for selecting a second clock of the nearest phase to the reference clock signal out of two or more second clock signals different in phase according to the selection signal from the initial phase difference detector at the initial signal inputting time, and outputting the second clock as a third clock signal; and a voltage-controlled variable delay line for outputting the first clock signal added with the phase delay according to the signal from the phase comparator, to the third clock signal. <P>COPYRIGHT: (C)2010,JPO&INPIT |
