发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a pattern forming method without causing a misregistration of a pair space pattern in a trench gate forming. <P>SOLUTION: A third to first mask layers 13, 12, 11 are layered on a layer 1 to be processed in order. A fourth mask layer is formed on the first mask layer, and the first mask layer is formed in a line pattern shape with the fourth mask layer as a mask. A sidewall layer 21a is formed on both the sides in the direction of line width of the first mask layer, then the first mask layer is removed. The second mask layer is formed in a pair of line pattern shape with the pair of the sidewall layers as a mask. A fifth mask layer is formed on the third mask layer, and a pair of openings are located on the third mask layer with the fifth mask layer as a mask. A pair of grooves are located on the layer to be processed layer with the third mask layer as a mask. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010080944(A) 申请公布日期 2010.04.08
申请号 JP20090194581 申请日期 2009.08.25
申请人 ELPIDA MEMORY INC 发明人 SUGIMURA TAKASHI
分类号 H01L21/28;H01L21/3205;H01L21/8242;H01L27/108;H01L29/423;H01L29/49 主分类号 H01L21/28
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