| 摘要 |
A memory access controller is disclosed. A packet memory stores a packet and has a clock parallel outputting function of parallel-outputting first data and a clock. A read controller reads the first data. A clock transfer unit performs a clock transfer operation by writing the first data using the clock and reading second data using a system clock. A packet assembly unit receives the second data and reassembles the packet. An information memory stores a read start address where head data of the packet is stored and packet length information indicating a length of the packet. A read controller receives the read start address and the packet length information, generates a read address necessary for reading one packet, and reads the first data from the packet memory.
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