| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To correct timing deviation in memory-side multi-phase clock signals. <P>SOLUTION: A semiconductor device includes a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and the data output circuit fetches data in response to multi-phase clock signals having different phases to be timing signals for fetching data, and adjusts a valid range for fetching data to be substantially uniform for each of the multi-phase clock signals. The window width of data can be made uniform by individually adjusting the multi-phase clock signals that are input or output timing signals, and thus characteristics of the semiconductor device can be improved. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
