发明名称 PROCESSOR ARRAY AND ITS FORMATION METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To provide high-degree connectivity between process elements within a parallel array of processors, while minimizing wires necessary to mutually connect the process elements, and communication latencies which communications between PEs encounter. <P>SOLUTION: A manifold array topology includes the process elements set in array in a cluster 52, nodes, a memory, and the like. The cluster is connected by a cluster switch configuration 986A for enabling advantageous change of structure without physically rearranging the process elements. The general number of mutual interconnection parts for the existing array can be reduced, and high-speed, efficient, and cost effective process and communication are obtained while accompanying an additional merit of easy scalability. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2010079912(A) 申请公布日期 2010.04.08
申请号 JP20090240821 申请日期 2009.10.19
申请人 ALTERA CORP 发明人 PECHANEK GERALD G;PITSIANIS NIKOS P;BARRY EDWIN F;DRABENSTOTT THOMAS L
分类号 G06F15/173;G06F15/80 主分类号 G06F15/173
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