| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an abstraction device and a verification device of circuit description, an abstraction program and a verification program of the circuit description, and an abstraction method and a verification method of the circuit description, allowing facilitation of verification of the circuit description converted into a formal specification, wherein description contents of a computer program can be verified by formal technique. Ž<P>SOLUTION: The abstraction device determines whether each calculation processing unit included in a logic model shown by specification data 24 of the circuit description is a non-verifiable calculation processing unit not allowing the verification by the formal technique within a preset threshold time. When decision results are affirmative decision, a list of verifiable calculation processing units allowing the verification by the formal technique within the threshold time is output to an output device 13 in a selectable state based on input operation from an input device 12. Inside the logic model, the calculation processing unit decided that it is the unverifiable calculation processing unit is replaced with the calculation processing unit selected from the list of the verifiable calculation processing units. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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