| 摘要 |
This invention generally relates to signal generation, clock signal generation and ramp signal generation, and trimming the temperature coefficient of a signal. Signal generator circuit, comprising: a capacitive element; a FET, arranged to generate current through the drain thereof and to supply to or from the capacitive element a current substantially equal to said drain current; and a bias voltage generator arranged to provide a bias voltage to the gate of the FET, wherein: the capacitance per unit area of the capacitive element and the capacitance per unit area of the gate of the FET are substantially equal; the bias voltage generator is arranged to generate a bias voltage substantially equal to a sum of a first voltage and a second voltage; said first voltage is arranged to be substantially proportional to a reference voltage; said second voltage is arranged to be substantially proportional to temperature; and the voltage between the source and gate of the FET is arranged to be substantially equal to the sum of the bias voltage and a gate threshold voltage of the FET.
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