| 摘要 |
Provided is a method that includes forming first and second gate structures in first and second regions, respectively, the first gate structure including a first hard mask layer having a first thickness and the second gate structure including a second hard mask layer having a second thickness less than the first thickness, removing the second hard mask layer from the second gate structure, forming an inter-layer dielectric (ILD) over the first and second gate structures, performing a first chemical mechanical polishing (CMP), remove the silicon layer from the second gate structure thereby forming a first trench, forming a first metal layer to fill the first trench, performing a second CMP, remove the remaining portion of the first hard mask layer and the silicon layer from the first gate structure thereby forming a second trench, forming a second metal layer to fill the second trench, and performing a third CMP.
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