| 摘要 |
A power-on circuit which may generate a power-on signal that is insensitive to the rising speed of an I/O voltage or core voltage. A power-on signal may be generated according to current drive capabilities of NMOS and PMOS transistors based on the I/O voltage or core voltage. A power-on circuit may control an I/O voltage when the level of a core voltage is lower than the I/O voltage. |
