<p>A memory interface (102) includes: a first data latch unit (103) which delays a strobe signal from a memory device (101) via a first variable delay unit (104) and reads the signal as a first data signal; and a second data latch unit (106) which delays the strobe signal via a second variable delay unit (107) and reads the signal as a second data signal for observing the delay. The data read by the first data latch unit (103) is used for normal memory access operation and compared to the data read by the second data latch unit (106) so as to detect the limit of the delay amount, which is reflected in the delay amount of the first variable delay unit (104). Thus, it is possible to correct the delay amount without interrupting the normal memory access operation.</p>
