发明名称 |
Mold array process for semiconductor packages |
摘要 |
A mold array process (MAP) for manufacturing a plurality of semiconductor packages is revealed. Firstly, a substrate strip including a plurality of substrate units arranged in an array within a molding area is provided. A plurality of chips are disposed on the substrate units. An encapsulant by molding is formed on the molding area of the substrate strip to continuously encapsulate the chips. During the molding process, an adjustable top mold is implemented where a cavity width between two opposing sidewalls inside a top mold chest can be adjusted to make the mold flow speeds at the center and at the side rails of the molding area the same.
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申请公布号 |
US7691676(B1) |
申请公布日期 |
2010.04.06 |
申请号 |
US20080271435 |
申请日期 |
2008.11.14 |
申请人 |
POWERTECH TECHNOLOGY INC. |
发明人 |
FAN WEN-JENG;FANG LI-CHIH;LIN JI-CHENG |
分类号 |
H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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