发明名称 Stacked-die packages with silicon vias and surface activated bonding
摘要 In some embodiments, an apparatus and a system are provided. The apparatus and the system may comprise a first integrated circuit die comprising a plurality of silicon vias and a first surface activated bonding site coupled to the plurality of silicon vias, and a second integrated circuit die comprising a second surface activated bonding site coupled to the first surface activated bonding site. The first surface activated bonding site may comprise a first clean metal and the second surface activated bonding site may comprise a second clean metal. If the first surface activated bonding site is coupled to the second surface activated bonding site respective metal atoms of the first activated surface activated bonding site are diffused into the second surface activated bonding site and respective metal atoms of the second activated surface activated bonding site are diffused into the first surface activated bonding site.
申请公布号 US7692278(B2) 申请公布日期 2010.04.06
申请号 US20060642293 申请日期 2006.12.20
申请人 INTEL CORPORATION 发明人 PERIAMAN SHANGGAR;OOI KOOI CHI;CHEAH BOK ENG
分类号 H01L23/31;H01L23/48;H01L23/498;H01L23/538 主分类号 H01L23/31
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